Download 60-GHz CMOS Phase-Locked Loops by Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund PDF

By Hammad M. Cheema, Reza Mahmoudi, Arthur H.M. van Roermund

The promising excessive facts cost instant functions at millimeter wave frequencies as a rule and 60 GHz particularly have won a lot consciousness in recent times. even though, demanding situations with regards to circuit, format and measurements in the course of mm-wave CMOS IC layout must be triumph over sooner than they could turn into practicable for mass market.

60-GHz CMOS Phase-Locked Loops targeting phase-locked loops for 60 GHz instant transceivers elaborates those demanding situations and proposes recommendations for them. The procedure point layout to circuit point implementation of the whole PLL, besides separate implementations of person elements equivalent to voltage managed oscillators, injection locked frequency dividers and their mixtures, are incorporated. moreover, to meet a couple of transceiver topologies concurrently, flexibility is brought within the PLL structure through the use of new dual-mode ILFDs and switchable VCOs, whereas reusing the low frequency elements on the related time.

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As an example, consider a measurement of an oscillator operating in the V-band (50–75 GHz). As there is no single-box PSA available operating above 50 GHz, external mixers have to be employed to extend the frequency range to the desired band. A typical measurement setup is shown in Fig. 12. These harmonic mixers exhibit frequency dependent loss which is difficult to calibrate. The result is an increase in the noise floor of the spectrum analyzer as well as un-calibrated output power levels. Consequently, phase noise of the oscillator becomes increasingly difficult to measure.

0 100 Fig. 3 pF) required for an oscillator as a function of frequency one-tool which can do-it-all. Therefore, a number of different simulation and extraction tools are utilized to accomplish the task. A typical IC design flow is shown in Fig. 2. It is to be noted, as will be explained shortly, that the steps inside the dashed box are more critical in a mm-wave design flow as compared to a low frequency design. In case the post-layout simulations, which usually include RC extraction from one tool and inductance extraction from EM-solvers, do not meet the required specifications, the layout has to be modified and subsequently the extraction has to be repeated.

The phase-frequency detector and charge-pump are merged into one block represented by a transfer parameter, KPFD (equal to Icp/2p). The impedance of the second-order loop filter is shown as ZLPF. The VCO conversion gain, KVCO, represents the sensitivity of VCO frequency with tuning voltage in rad/(s  V). 00 fref KPFD Iout(s) 192 198 204 210 KVCO /s ZLPF(s) fbck C1 Vcont(s) fout C2 R1 ÷N Prescaler ÷P fout /P Fig. 8 Simplified s-domain representation of the synthesizer ratio of the prescaler and lower frequency divider chain is represented by P and N, respectively.

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